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boards:mantle

General

The mantle will consist of the implementation of the OrBit Core and add a useful array of peripherals/features for easy development

Connectivity

Features

  • Debugger connections
  • Micro-USB B connector
  • Debugging LED output
  • User Button
  • 50Ω SMA connector for Antenna
  • VDC input accept 5 to 55Vin
  • External Vin connection for battery or other sources

Schematic

Last version of the Schematic


IO/Module map suggestion

PORT_A
GPIO PeripheralPinReserved functionNote
A0 RF_GPIO0
A1 RF_GPIO1
A12TIMER_2CC0 [RED_LED]Can be disconnected (CCx = PWM)
A13TIMER_2CC1[GREEN_LED]Can be disconnected (CCx = PWM)
A14TIMER_2CC2[BLUE_LED]Can be disconnected (CCx = PWM)
PORT_B
GPIO PeripheralPinReserved functionNote
B3USART_2#1 MOSIauxiliary memory<Required by core>
B4USART_2#1MISO auxiliary memory<Required by core>
B5USART_2#1SCK auxiliary memory<Required by core>
B6USART_2#1CS auxiliary memory<Required by core> Not accessible
B7TIMER_1CC0 CCx = PWM
B8TIMER_1CC1 CCx = PWM
B11TIMER_1CC2 CCx = PWM
B13LEUART0TX[RS-485]
B14LEUART0RX[RS-485]
PORT_C
GPIO PeripheralPinReserved functionNote
C6GPIO Buton[Buton_C6]Internal pull-up need to be configured
C7GPIO Buton[Buton_C7]Internal pull-up need to be configured
PORT_D
GPIO PeripheralPinReserved functionNote
D0DAC_0out_2_0
D1ADC_0ch1
D2ADC_0ch2
D3ADC_0ch3
D4ADC_0ch4
D5DAC_0out_2_1
D6ADC_0ch6
D7ADC_0ch7
D8GPIO [RS-485_Tx_En]
PORT_E
GPIO PeripheralPinReserved functionNote
E0I2C_1SDA
E1I2C_1SCL
E2UART_1TX
E3UART_1RX
PORT_F
GPIO PeripheralPinReserved functionNote
F0JTAGSWCLK[JTAG]
F1JTAGSWDIO[JTAG]
F2JTAGSWO#0[JTAG]
F3TIMER_0CDTI0
F4TIMER_0CDTI1
F5TIMER_0CDTI2
F6TIMER_0CC0 CCx = PWM
F7TIMER_0CC1 CCx = PWM
F8TIMER_0CC2 CCx = PWM
boards/mantle.txt · Last modified: 2016/01/26 18:35 by laurencedv