====== General ======
The idea behind the Core is to provide a minimal design to implement a dedicated OrBit node tailored to a specific need. For this reason, it has been deliberately limited to bare minimal peripherals and IO.

[[https://git.megaxone.net/OrBit/Core|Developpement space]]

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====== Sub-Section ======
===== System-on-chip =====
The chosen SoC is an [[http://www.silabs.com/Support%20Documents/TechnicalDocs/EZR32WG330_DataSheet.pdf|EZR32WG330F256R61]]. Basically it's a Wonder Gecko with USB and a Si4461 transceiver in a single package.

===== Auxiliary Memory =====
There is a 4mbit SPI flash memory directly connected to the SoC used to store backup firmware and store a new firmware version for the bootloader. A part of it is also accessible by the application to store general usage data. We are looking into protecting the bootloader section, but for now it is not protected, BEWARE!

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====== Connectivity ======
===== USB connection =====
There is a 90Ω pair connected to the internal USB transceiver of the [[#System-on-chip|SoC]]. You can route it to a USB connector or anything that talk USB.

===== Programming =====
==== JTAG ====
We provide all the necessary connection for a Cortex-SWD JTAG connection. The official pin-out from ARM:

{{:electronic:project:orbit_network:cortex_swd_jtag_connector_pinout.png?direct&200 |}}
Use a 50mil 2x5 header connector like [[http://www.digikey.ca/product-detail/en/FTSH-105-01-F-DV/SAM8795-ND/|this]] to respect the standard.

==== Bootloader ====
A bootloader is present in the chip and use the external memory to store a backup image in addition to a new version that you can upload via **CHOOSE A PROTOCOL**.

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====== Features ======
  * Temperature tolerance: **-40˚C** to **85˚C** ambiant
  * USB Device connectivity
  * ±30ppm 30MHz oscillator

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====== Schematic ======
Last version of the [[https://git.megaxone.net/OrBit/Core/raw/master/doc/OrBit-Core.pdf|Schematic]]

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====== Usage ======
The Core design is used in the [[boards:mantle|Mantle board]].


====== IO/Module map (fixed) ======
^PORT_B^^^^^
^GPIO ^Peripheral^Pin^Reserved function^Note^
|B3|USART_2#1|MOSI |[auxiliary memory]|<Required by core>|
|B4|USART_2#1|MISO |[auxiliary memory]|<Required by core>|
|B5|USART_2#1|SCK  |[auxiliary memory]|<Required by core>|
|B6|USART_2#1|CS   |[auxiliary memory]|<Required by core> ((not available for other uses))|

For more IO information and suggestion check-out [[boards:mantle|the mantle board]]